GS2960 datasheet(39/97 Pages) SEMTECH

39 / 97 page

GS2960 3Gb/s, HD, SD SDI Receiver Complete with

SMPTE Video Processing

Data Sheet

48003 - 6

September 2012

39 of 97

An example delay adjustment over min/typ/max conditions is illustrated in Figure 4-8.

The target delay is 0.84 ns under typical conditions (approximately 45º PCLK phase

shift), and requires a control word setting of 0x0014 for address 0x006C.

Figure 4-8: Delay Adjustment Ranges

4.10 Timing Signal Generator

The GS2960 has an internal timing signal generator which is used to generate digital

FVH timing reference signals, to detect and correct certain error conditions and

automatic video standard detection.

The timing signal generator is only operational in SMPTE mode (SMPTE_BYPASS =

HIGH).

The timing signal generator consists of a number of counters and comparators operating

at video pixel and video line rates. These counters maintain information about the total

line length, active line length, total number of lines per field/frame and total active lines

per field/frame for the received video standard.

It takes one video frame to obtain full synchronization to the received video standard.

NOTE: Both 8-bit and 10-bit TRS words are identified by the device. Once

synchronization has been achieved, the timing signal generator continues to monitor

the received TRS timing information to maintain synchronization.

The timing signal generator re-synchronizes all pixel and line based counters on every

received TRS ID.

PCLK

6.734ns

3.367ns

offset [5] = 1 (90º phase shift)

1.684ns

0.842ns

Ranges:

PCLK

(MIN)

6.734ns

3.367ns

1.684ns

PCLK

(TYP)

PCLK

(MAX)

0.58ns

delay

0.84ns

delay

1.38ns

delay

90º phase shift

Typical 45º phase shift

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