54F676DM datasheet(2/10 Pages) NSC

2 / 10 page

Logic Symbols

TLF9588 – 1

IEEEIEC

TLF9588 – 4

Unit LoadingFan Out

54F74F

Pin Names

Description

Input IIH IIL

HIGHLOW

Output IOH IOL

P0–P15

Parallel Data Inputs

1010

20 mA b06 mA

Chip Select Input (Active LOW)

1010

20 mA b06 mA

Clock Pulse Input (Active LOW)

1010

20 mA b06 mA

Mode Select Input

1010

20 mA b06 mA

Serial Data Input

1010

20 mA b06 mA

Serial Output

50333

1 mA20 mA

Functional Description

The 16-bit shift register operates in one of three modes as

indicated in the Shift Register Operations Table

HOLD

a HIGH signal on the Chip Select (CS) input pre-

vents clocking and data is stored in the sixteen registers

ShiftSerial Load

data present on the SI pin shifts into

the register on the falling edge of CP Data enters the Q0

position and shifts toward Q15 on successive clocks finally

appearing on the SO pin

Parallel Load

data present on P0–P15 are entered into

the register on the falling edge of CP The SO output repre-

sents the Q15 register output

To prevent false clocking CP must be LOW during a LOW-

to-HIGH transition of CS

Shift Register Operations Table

Control Input

Operating Mode

MCP

Hold

ShiftSerial Load

Parallel Load

H e HIGH Voltage Level

L e LOW Voltage Level

X e Immaterial

K e HIGH-to-LOW Transition

Block Diagram

TLF9588 – 5

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