UT699CPC datasheet(23/41 Pages) AEROFLEX

부품명	UT699CPC

상세설명	UT699 32-bit Fault-Tolerant SPARCTM V8/LEON 3FT Processor

PDF	41 Pages

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4.0 Timing Specifications

4.1 Power Sequencing and Reset

(VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40

oC to 105oC)

Notes:

1. Guaranteed by design.

2. Guaranteed by design for control signals.

Symbol

Description

Conditions

Min

Max

Units

tVCD

VDD valid to VDDC delay

VDD > 3.0V; VDDC > 2.30V

tVHBZ

VDD valid to control signals high-Z

(WRITE, OE, IOS, ROMS[1:0],

RWE[3:0], RAMOE [4:0], READ

SDWE, and SDCS[1:0])

VDD valid to outputs high-Z

([DATA[31:0], CB[7:0], and GPIO[15:0])

VDD > 1.5V; VDDC = 0V

tCLK

tCHBV

VDDC valid to control signals valid-inac-

tive

(WRITE, OE, IOS, ROMS[1:0],

RWE[3:0], RAMOE [4:0], READ

SDWE, and SDCS[1:0])

VDD > 3.0V; VDDC > 2.30V

tCLK

tRESET1

VDDC valid to RESET deassert

VDDC > 2.30V

tCLK

tRESET2

RESET deasserted to outputs valid-active

(ROMS[0] and OE)

tCLK

tRESET3

RESET asserted to control signals valid-

inactive

(WRITE, OE, IOS, ROMS[1:0],

RWE[3:0], RAMOE [4:0], READ

SDWE, and SDCS[1:0])

RESET asserted to outputs high-Z

(DATA[31:0], CB[7:0], and GPIO[15:0])

tCLK

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