Unit LoadingFan Out

54F74F

Pin Names

Description

UL

HIGHLOW

Data Inputs

1010

OE

Output Enable

1010

TRI-STATE Input

CP

Clock Input

1010

TRI-STATE Outputs

15040 (333)

b

30 mA24 mA (20 mA)

Functional Description

The ’F821 consists of ten D-type edge-triggered flip-flops

This device has TRI-STATE true outputs for bus systems

organized in a broadside pinning The buffered Clock (CP)

and buffered Output Enable (OE) are common to all flip-

flops The flip-flops will store the state of their individual D

inputs that meet the setup and hold times requirements on

the LOW-to-HIGH CP transition With the OE LOW the con-

tent of the flip-flops are available at the outputs When the

OE is HIGH the outputs go to the high impedance state

Operation of the OE input does not affect the state of the

flip-flops

Function Table

Inputs

Internal

Output

Function

OE

CP

D

Q

O

H

H

X

NC

Z

Hold

H

L

X

NC

Z

Hold

H

L

L

H

Z

Load

H

L H

L

Z

Load

L

L

L

H

L

Data Available

L

L H

L

H

Data Available

L

H

X

NC

NC

No Change in Data

L

L

X

NC

NC

No Change in Data

Logic Diagram

TLF9595 – 4

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays

2