2

Aeroflex Microelectronics Solutions - HiRel

36-00-00-001

Ver. 1.5.0

1.0 Introduction

The UT699E LEON 3FT processor is based upon the industry-standard SPARC V8 architecture. The system-on-chip incorporates

the SPARC V8 core and the peripheral blocks indicated below. The core and peripherals communicate internally via the AMBA

(Advanced Microcontroller Bus Architecture) interconnect. This bus is comprised of the AHB (Advanced High-speed Bus) which is

used for high-speed data transfer, and the APB (Advanced Peripheral Bus) which is used for low-speed data transfer.

Figure 1. UT699E Functional Block Diagram

The LEON 3FT architecture includes the following peripheral blocks:

•

LEON3 SPARC V8 integer unit with 16kB instruction cache and 16kB of data cache

•

IEEE-754 floating point unit

•

Debug support unit

•

UART, JTAG, SpaceWire, and PCI debug links

•

8/16/32-bit memory controller with EDAC for external PROM and SRAM

•

32-bit SDRAM controller with EDAC for external SDRAM

•

Timer unit with three 32-bit timers and watchdog

•

Interrupt controller for 15 interrupts in two priority levels

•

16-bit general purpose I/O port (GPIO) which can be used as external interrupt sources

•

Up to four SpaceWire links with RMAP on all channels

•

Up to two CAN controllers

•

Ethernet with support for MII

•

cPCI interface with 8-channel arbiter

AMBA AHB

Timers

IrqCtrl

AMBA APB

8/16/32-bits memory bus

Debug

Support Unit

AHB interface

LEON 3FT

Memory

Controller

AHB/APB

Bridge

I/O port

UART

IEEE754

FPU

MUL/DIV

MMU

PCI

CAN-2.0

AHB Ctrl

Serial/JTAG

Debug Link

4x SpW

Bridge

Ethernet

MAC

D-cache

4x4K

I-cache

512 MB

PROM

256 MB

I/O

Up t o1GB

SRAM

4x4K

D-cache

Up to 1GB

SDRAM