ICS1524

14

ICS1524 Rev C 01/31/2003

RANDOM REGISTER WRITE PROCEDURE

S 010011x W A

A

A P

7 bit address

register address

data

Acknowledge

Acknowledge

STOP condition

START condition

WRITE command

Acknowledge

RANDOM REGISTER READ PROCEDURE

S 010011 X W A

A S 0 10011 X R A

A P

7 bit address

register address

7 bit address

data

Acknowledge

Repeat START

Acknowledge

STOP condition

START condition

WRITE command

Acknowledge

READ command

NO Acknowledge

SEQUENTIAL REGISTER WRITE PROCEDURE

S 010011 X W A

A

A

A

A P

7 bit address

register address

data

data

Acknowledge

Acknowledge

Acknowledge

Acknowledge Acknowledge

START condition

WRITE command

STOP condition

SEQUENTIAL REGISTER READ PROCEDURE

S 010011 X W A

A S 0 10011 X R A

A

A P

7 bit address

register address

7 bit address

data

data

Acknowledge

Repeat START

Acknowledge

NO Acknowledge

START condition

WRITE command

Acknowledge

READ command

Acknowledge STOP condition

Direction:

From bus host to device

From device to bus host

Note:

1. All values are transmitted with the most-significant bit first and the least-significant bit last.

3. R = READ = 1 and W = WRITE = 0