6.42

18

IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous

Commercial and Industrial Temperature Ranges

SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect

CLK

ADSP

GW,BWE,BWx

ADDRESS

ADSC

OE

Av

Aw

Ax

Ay

Az

(Av)

(Aw)

(Ax)

(Ay)

5311 drw 14

,

Non-Burst Read Cycle Timing Waveform

NOTES:

1. ZZ input is LOW,

ADV is HIGH and LBO is Don't Care for this cycle.

2. (Ax) represents the data for address Ax, etc.

3. For read cycles,

ADSP and ADSC function identically and are therefore interchangable.

NOTES:

1. ZZ input is LOW,

ADV and OE are HIGH, and LBO is Don't Care for this cycle.

2. (Ax) represents the data for address Ax, etc.

3. Although only

GW writes are shown, the functionality of BWE and BWx together is the same as GW.

4. For write cycles,

ADSP and ADSC have different limitations.

Non-Burst Write Cycle Timing Waveform

CLK

ADSP

GW

ADDRESS

ADSC

Av

Aw

Ax

Az

Ay

(Av)

(Aw)

(Ax)

(Az)

(Ay)

5311 drw 15

,