2

SCD4808N Rev B

FIGURE 1 – TRANSMITTER LOGIC WAVEFORMS IDEALIZED

FIGURE 2 – RECEIVER LOGIC WAVEFORMS IDEALIZED

DATA IN

DATA IN

INHIBIT

LINE TO LINE

OUTPUT

2. DATA and DATA inputs must be complementary waveforms or 50% duty cycle average, with no delays between them.

3. DATA and DATA must be in the same state during off time (both high or low).

1. Line to line waveforms illustrate Macair signals, MIL-STD-1553 signals are trapezoidal.

Note overlap

NOTE: Waveforms shown are for normally low devices. For normally high receiver output

devices, the receiver outputs are swapped as shown by the dashed lines.

level

LINE TO LINE

INPUT

DATA OUT

DATA OUT

BLOCK DIAGRAM (WITHOUT TRANSFORMER)

OUTPUT

STAGE

COMP.

COMP.

INPUT

AMP

DRIVER

TX DATA IN

TX DATA IN

TX INHIBIT

+5 V

RX DATA IN

RX DATA IN

STROBE

TX DATA OUT

TX DATA OUT

RX DATA OUT

RX DATA OUT

V+

V-

TRANSMIT

FILTER

ACTIVE

RECEIVE

FILTER

ACTIVE