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UT64BS1X433 데이터시트(PDF) 13 Page - Aeroflex Circuit Technology |
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UT64BS1X433 데이터시트(HTML) 13 Page - Aeroflex Circuit Technology |
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13 / 20 page ![]() 13 AC CHARACTERISTICS (Pre and Post-Radiation)* (VDD = 3.3V + 0.3V; VSS < VIN < VDD; -55°C < TC < +125°C); Unless otherwise noted, TC is per the temperature range ordered Notes: * For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25°C per MIL-STD-883 Method 1019, Condition A up to the maximum TID level procured. 1. Not tested. The propagation delay through the channel is based upon the RC time constant of the maximum channel resistance and switch ON capacitance; 11 Ω and 17pF. SYMBOL DESCRIPTION CONDITIONS MIN MAX UNITS tP,BUS1 Bussed signals propagation delay From any mA input to any mBn output -- 187 ps tON1 Bussed signals ON time From BANK to any mBn output; ROMS and RAMS static RL=50Ω, CL=50pF 1.7 6.2 ns tOFF1 Bussed signals OFF time From BANK to any mBn output; ROMS and RAMS static RL=50Ω, CL=50pF 1.7 5.7 ns tON2 Bussed signals ON time From ROMS or RAMS to any mBn out- put; BANK static RL=50Ω, CL=50pF 1.7 6.2 ns tOFF2 Bussed signals OFF time From ROMS or RAMS to any mBn out- put; BANK static RL=50Ω, CL=50pF 1.7 5.7 ns tPLH1 Logic output low-to-high delay From ASEL, BSEL, or BANK to any CS; ROMS and RAMS static RL=50Ω, CL=50pF 2.0 7.5 ns tPHL1 Logic output high-to-low delay From ASEL, BSEL, or BANK to any CS; ROMS and RAMS static RL=50Ω, CL=50pF 2.0 7.5 ns tPLH2 Logic output low-to-high delay From ROMS or RAMS to any CS; ASEL, BSEL, and BANK static RL=50Ω, CL=50pF 2.0 7.5 ns tPHL2 Logic output high-to-low delay From ROMS or RAMS to any CS; ASEL, BSEL, and BANK static RL=50Ω, CL=50pF 2.0 7.5 ns tPLH3 Buffered output low-to- high delay From XIN to any XOUT or YIN to any YOUT RL=50Ω, CL=50pF 1.0 4.0 ns tPHL3 Buffered output high-to- low delay From XIN to any XOUT or YIN to any YOUT RL=50Ω, CL=50pF 1.0 4.0 ns 36-00-03-001 Aeroflex Microelectronics Solutions - HiRel |
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