LXT351 datasheet(39/46 Pages) INTEL

39 / 46 page

T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351

Datasheet

Table 30. 20 MHz Intel Bus Parallel I/O Timing Characteristics (See Figure 16)

Parameter

Sym

Min

Max

Unit

Test Conditions

ALE pulse width

TLHLL

–

Address valid to ALE falling edge

TAVLL

–

ALE falling edge to address hold time

TLLAX

–

ALE falling edge to RD falling edge

TLLRL

–

ALE falling edge to WR falling edge

TLLWL

–

CS falling edge to RD falling edge

TCLRL

–

CS falling edge to WR falling edge

TCLWL

–

RD Low pulse width

TRLRH

–

RD falling edge to data valid

TRLDV

Data hold time after RD rising edge

TRHDX

535

RD rising edge to ALE rising edge

TRHLH

–

RD rising edge to address valid

TRHAV

–

CS Low hold time after RD rising edge

TRHCH

–

WR Low pulse width

TWLWH

–

Data setup time before WR rising edge

TDVWH

–

Data hold time after WR rising edge

TWHDX

–

WR rising edge to ALE rising edge

TWHLH

–

CS Low hold time after WR rising edge

TWHCH

–

LXT351 데이터시트(PDF) 39 Page - Intel Corporation

LXT351 데이터시트(HTML) 39 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

데이터시트 다운로드

링크 URL