LXT972ALC datasheet(22/70 Pages) INTEL

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LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet

Datasheet

3.4.3

Reduced Power Modes

The LXT972A offers two power-down modes.

3.4.3.1

Hardware Power Down

The hardware power-down mode is controlled by the PWRDWN pin. When PWRDWN is High,

the following conditions are true:

• The LXT972A network port and clock are shut down.

• All outputs are tri-stated.

• All weak pad pull-up and pull-down resistors are disabled.

• The MDIO registers are not accessible.

3.4.3.2

Software Power Down

Software power-down control is provided by bit 0.11 in the Control Register (refer to Table 37 on

page 58). During soft power-down, the following conditions are true:

• The network port is shut down.

• The MDIO registers remain accessible.

Figure 6. Initialization Sequence

MDDIS Voltage

Level?

High

Low

MDIO Control

Mode

Hardware Control

Mode

Disable MDIO Read and

Write Operations

Reset MDIO Registers to

values read at H/W

Control Interface at last

Hardware Reset

MDIO Controlled Operation

(MDIO Writes Enabled)

Power-up or Reset

Initialize MDIO Registers

Read H/W Control

Interface

Software

Reset?

Yes

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