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AX88796LF 데이터시트(PDF) 55 Page - ASIX Electronics Corporation

부품명 AX88796LF
상세설명  3-in-1 Local Bus Fast Ethernet Controller
PDF  71 Pages
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제조업체  ASIX [ASIX Electronics Corporation]
홈페이지  http://www.asix.com.tw
Logo ASIX - ASIX Electronics Corporation

AX88796LF 데이터시트(HTML) 55 Page - ASIX Electronics Corporation

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ASIX ELECTRONICS CORPORATION
55
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
7.4 A.C. Timing Characteristics
7.4.1 XTAL / CLOCK
LCLK/XTALIN
Tr
Tf
Tlow
CLKO
Tod
Symbol
Description
Min
Typ.
Max
Units
Tcyc
CYCLE TIME
40
ns
Thigh
CLK HIGH TIME
16
20
24
ns
Tlow
CLK LOW TIME
16
20
24
ns
Tr/Tf
CLK SLEW RATE
1
-
4
ns
Tod
LCLK/XTALIN TO CLKO OUT DELAY
10
7.4.2 Reset Timing
LCLK/XTALIN
RESET
/RESET
Symbol
Description
Min
Typ.
Max
Units
Trst
Reset pulse width
100
-
-
LClk
Warning: Some chips may needed long power down for successful PHY auto
negotiation
Root of cause:
The PHY inside of AX88796 has a special request due to the semiconductor’s process. Namely,
it needs a very long power down for successful Auto Negotiation for some chips. We made a test
in lab and found it would be no problem if the PHY's initial time kept for 2 sec for all chips. If the
power down is less then this number, some of the PHY's Auto Negotiation will not be complete
and there will be potential to cause the link fail. If the auto negotiation time is not long enough,
uncertain numbers of chip may not work properly.
Tcyc
Thigh



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