TLF5948

June 1996

CD4015BMCD4015BC Dual 4-Bit Static Shift Register

General Description

The CD4015BMCD4015BC contains two identical 4-stage

serial-inputparallel-output

registers

with

independent

‘‘Data’’ ‘‘Clock’’ and ‘‘Reset’’ inputs The logic level pres-

ent at the input of each stage is transferred to the output of

that stage at each positive-going clock transition A logic

high on the ‘‘Reset’’ input resets all four stages covered by

that input All inputs are protected from static discharge by a

Features

Y

Wide supply voltage range

30V to 18V

Y

High noise immunity

Y

Low power TTL

Fan out of 2 driving 74L

compatibility

or 1 driving 74LS

Y

Medium speed operation

8 MHz (typ) clock rate

Y

Fully static design

Applications

Y

Serial-inputparallel-output data queueing

Y

Serial to parallel data conversion

Y

General purpose register

Connection Diagram and Truth Table

Dual-In-Line Package

TLF5948 – 1

L 00

0

L 10

1

(No change)

XX

1

0

0

U

Level change

Order Number CD4015B

C1996 National Semiconductor Corporation

RRD-B30M76Printed in U S A

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