TLF5962

February 1988

CD4031BMCD4031BC

64-Stage Static Shift Register

General Description

The CD4031BMCD4031BC is an integrated complemen-

tary MOS (CMOS) 64-stage fully static shift register Two

data inputs DATA IN and RECIRCULATE IN and a MODE

CONTROL input are provided Data at the DATA input

(when MODE CONTROL is low) or data at the RECIRCU-

LATE input (when MODE CONTROL is high) which meets

the setup and hold time requirements is entered into the

first stage of the register and is shifted one stage at each

positive transition of the CLOCK

Data output is available in both true and complement forms

from the 64th stage Both the DATA OUT (Q) AND DATA

OUT (Q) outputs are fully buffered

The CLOCK input of the CD4031BMCD4031BC is fully

buffered and present only a standard input load capaci-

been provided to allow reduced clock drive fan-out and tran-

sition time requirements when cascading packages

Features

Y

Wide supply voltage range

30V to 15V

Y

High noise immunity

Y

Low power TTL

fan out of 2 driving 74L

compatibility

or 1 driving 74LS

Y

Fully static operation

DC to 8 MHz

Y

Fully buffered clock input

5 pF (typ)

input capacitance

Y

Single phase clocking requirements

Y

Delayed clock output for reduced clock drive require-

ments

Y

Fully buffered outputs

Y

High current sinking capability

16 mA

Y

Q output

Logic and Connection Diagrams

TLF5962 – 1

Dual-In-Line Package

TLF5962 – 2

Top View

Order Number CD4031B

C1995 National Semiconductor Corporation

RRD-B30M105Printed in U S A