Shift RightShift Left with Parallel Inputs

TLF5963 – 15

Shift left input must be disabled during parallel entry

A ‘‘High’’ (‘‘Low’’) on the Shift LeftShift Right input allows

serial data on the Shift Left Input (Shift Right Input) to enter

the register on the positive transition of the clock signal A

‘‘high’’ on the ‘‘A’’ Enable Input disables the ‘‘A’’ parallel

data lines on Registers 1 and 2 and enables the ‘‘A’’ data

lines on Registers 3 and 4 and allows parallel data into Reg-

isters 1 and 2 Other logic schemes may be used in place of

registers 3 and 4 for parallel loading

When parallel inputs are not used Registers 3 and 4 and

associated logic are not required

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