2–17

Table 2–6. External Pins Mapping to S[3:0] in VIDSTA Register

PIN

VIDSTA REGISTER

COMMENTS

NO.

NAME

S[3:0]

COMMENTS

58

P3.0

S0

Dual function P3.0 I/O or S0 input

57

P3.1

S1

Dual function P3.1 I/O or S1 input

8

S2

S2

S2-pin is input

9

S3

S3

S3-pin is input

2.7

Function Reset and Power-Up Reset Interconnect

Figure 2–3 represents the logical connection of USB-function-reset (USBR) and power-up-reset (RST-pin). The

internal RESET signal is generated from the RST pin (PURS signal) or from the USB-reset (USBR signal). The USBR

can be enabled or disabled by the FRSTE bit in the USBCTL register (on power up FRSTE is = 0). The internal RESET

is used to reset all registers and logic, with the exception of the USBCTL and MISCTL registers. The USBCTL and

MCU configuration register (MCNFG) are cleared by PURS signal only.

WDT Reset

WDE

PURS

USBCTL Register

MCNFG Register

USB Function Reset

FRSTE

RESET

MCU

All Internal MMR

RST

USBR

Figure 2–3. Reset Diagram