4–2

3.3 V

1.5 k

Ω

D+

D–

DP0

DM0

1.5 k

Ω

D+

D–

DP0

DM0

Bus PWR

(5 V)

PUR

(a)

(b)

Figure 4–3. Upstream Connection (a) Non-Switching Power Mode (b) Switching Power Mode

15 k

Ω

D+

D–

DP1

DM1

15 k

Ω

R1

R2

5 V

GND

To Power Switch

NOTE: Ferrite beads can be used on power lines to help ESD.

Figure 4–4. Downstream Connection – (Only One Port Shown)

4.2

Reset Timing

There are two requirements for the reset signal timing. First, the reset window should be between 100

msec and 10

msec. At power up, this time is measured from the time the power ramps up to 90% of the nominal Vcc until the reset

signal goes high (above 1.2 V). The second requirement is that the clock has to be valid during the last 60

msec of

the reset window. These two requirements are depicted in Figure 4–5. Notice that when using a 12 MHz crystal or

the 48 MHz oscillator, the clock signal may take several milliseconds to ramp up and become valid after power up.

Therefore, the reset window may need to be elongated up to 10 msec. to ensure that there is a 60

msec overlap with

a valid clock.

CLK

RESET

t

VCC

90%

3.3 V

1.2 V

0 V

>60

µs

100

µs < RESET TIME < 10 ms

Figure 4–5. Reset Timing