AD6676EBZ datasheet(38/90 Pages) AD

38 / 90 page

AD6676

Data Sheet

Rev. A | Page 38 of 90

DIGITAL PROCESSING BLOCKS

The AD6676 includes the following digital blocks between the

Σ-Δ ADC output and JESD204B transmitter core:

•

An ADC overload and recovery block immediately follows

the ADC. This circuitry quickly detects any ADC instability

from an overload event while ensuring fast recovery.

•

A digital signal processing block translates the real IF

signal from the Σ-Δ ADC to a complex zero IF, suitable for

postprocessing by the host without loss of any dynamic

range. This block includes both coarse and fine QDDCs,

along with a selectable FIR decimation filter stage that

provides decimation factors of 12, 16, 24, and 32.

•

A peak detection and AGC support block facilitates the

implementation of an external AGC control loop under the

control of the host. Note that the AGC pins can also be

repurposed for GPIO functions.

Figure 103 shows a diagram of the digital functional blocks

along with the SPI configurable registers pertaining to these

blocks. The following sections provide more insight into the

operation of each of these functional blocks. More information

pertaining to these SPI registers can be found in Table 32 through

Table 133.

BAND-PASS

Σ-Δ ADC

AGC

SUPPORT

AGC4, AGC3

AGC2, AGC1

REG 0x193

TO 0x19E

RESET

PEAK DETECTOR INPUT

ADC

OVERLOAD

RECOVERY

MIX1

COARSE

QDDC

NCO

REG 0x141

REG 0x143

MIX2

FINE

QDDC

NCO

REG 0x142

REG 0x144

REG 0x145

5 BITS

2×

16 BITS

2×

16 BITS

27dB ATTENUATOR

(1dB STEPS)

2×

3×

OR 4×

REG 0x188

TO 0x18B,

0x18F

GPIO CONTROL OPTION

REG 0x1B0

TO 0x1B4

ATTENUATOR CONTROL

REG 0x180 TO 0x184

DEC_MODE =

12, 16, 24 OR 32

REG 0x140

Figure 103. Simplified Block Diagram of Digital Processing Blocks

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