AD9993BBCZRL datasheet(39/56 Pages) AD

39 / 56 page

Data Sheet

AD9993

Rev. A | Page 39 of 56

INTEGER VALUE OF SYNTHESIZER DIVIDER REGISTER

Address: 0x031, Reset: 0x40, Name: SYNTH_INT

Table 30. Bit Descriptions for SYNTH_INT

Bits

Bit Name

Description

Reset

Access

[7:0]

SYNTH_INT

Integer part on the synthesizer divider (N). N = freq (MHz)/31.25.

0x40

SYNTHESIZER CONTROL REGISTER

Address: 0x032, Reset: 0x00, Name: SYNTH_CTRL

Table 31. Bit Descriptions for SYNTH_CTRL

Bits

Bit Name

Description

Reset

Access

SYNTH_CAL_START

Start synthesizer calibration.

0x0

SYNTH_CP_CAL_EN

Enable charge pump calibration.

0x0

CLOCK GENERATOR CONTROL REGISTER

Address: 0x033, Reset: 0x00, Name: CLKGEN_CTRL1

Table 32. Bit Descriptions for CLKGEN_CTRL1

Bits

Bit Name

Description

Reset

Access

CLKGEN_DC_MODE

DAC clock direct connect to ADC.

0x0

0 = ADC clock from 1 GHz.

1 = ADC clock from DAC.

CLKGEN_DC_MODE_INV

Not used.

0x0

CLKGEN_REFCLK_DIV1

0 = select REFCLK as PLL reference.

0x0

1 = select REFCLK/2 as PLL reference.

CLKGEN_REFDIV_EN

Selects the output of the on-chip reference clock divider to the PLL.

0x0

[1:0]

CLKGEN_REFDIV_SEL

Sets the divider ratio for the on-chip reference clock divider.

0x0

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