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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ADuC7122BBCZ 데이터시트(PDF) 13 Page - Analog Devices |
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ADuC7122BBCZ 데이터시트(HTML) 13 Page - Analog Devices |
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13 / 96 page  Data Sheet ADuC7122 Rev. A | Page 13 of 96 Table 7. SPI Slave Mode Timing (SPICPH = 0) Parameter Description Min Typ Max Unit t A CSE A CSE A to SCLOCK edge 200 ns tSL SCLOCK low pulse width1 (SPIDIV + 1) × tUCLK ns tSH SCLOCK high pulse width1 (SPIDIV + 1) × tUCLK ns tDAV Data output valid after SCLOCK edge 25 ns tDSU Data input setup time before SCLOCK edge1 1 × tUCLK ns tDHD Data input hold time after SCLOCK edge1 2 × tUCLK ns tDF Data output fall time 5 12.5 ns tDR Data output rise time 5 12.5 ns tSR SCLOCK rise time 5 12.5 ns tSF SCLOCK fall time 5 12.5 ns tDOCS Data output valid after A CSE A edge 25 ns tSFS A CSE A high after SCLOCK edge 0 ns 1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. MSB IN BITS 6 TO 1 LSB IN MSB BITS 6 TO 1 LSB MOSI MISO SCLOCK (POLARITY = 0) SCLOCK (POLARITY = 1) tSF tSFS tSR tSL tDAV tSH tDF tDR tDSU tDOCS tDHD CS tCS Figure 6. SPI Slave Mode Timing (SPICPH = 0) |
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