SP3203 datasheet(9/14 Pages) SIPEX

9 / 14 page

Rev. 6/25/03

SP3203

duces –VCC in the negative terminal of C1, which

is applied to the negative side of capacitor C2.

Since C2+ is at VCC, the voltage potential across

C2 is 2 times VCC.

VDD Transfer-Phase 4 (Figure 16)

The fourth phase of the clock connects the nega-

tive terminal of C2 to GND, and transfers this

positive generated voltage across C2 to C4, the

VDD storage capacitor. This voltage is regulated

to +5.5V. At this voltage, the internal oscillator

is disabled. Simultaneous with the transfer of the

voltage to C4, positive side of capacitor C1 is

switched to VCC and the negative side is con-

nected to GND, allowing the charge pump cycle

to begin again. The charge pump cycle will

continue as long as the operational conditions for

the internal oscillator are present.

Since both V+ and V– are separately generated

from VCC, in a no–load condition, V+ and V– will

be symmetrical. Older charge pump approaches

that generate V– from V+ will show a decrease in

the magnitude of V– compared to V+ due to the

inherent ineffiencies in the design.

The clock rate for the charge pump is typically

operates at 250kHz. The external capacitors are

usually 0.1

µF with a 16V breakdown voltage

rating.

VL Supply Level

Current RS-232 serial tranceivers are designed

with fixed 5V or 3.3V TTL input/output voltages

levels. The VL function in the SP3203 allows the

end user to set the TTL input/output voltage

levels independent of VCC. By connecting VL to

the main logic bus of system, the TTL input/

output limits and threshold are reset to interface

with the on board low voltage logic circuity.

)

((

µ )

SP3203 데이터시트(PDF) 9 Page - Sipex Corporation

SP3203 데이터시트(HTML) 9 Page - Sipex Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14

데이터시트 다운로드

링크 URL