SP385ECA datasheet(6/11 Pages) SIPEX

6 / 11 page

Rev. 10/22/01

SP385E Enhanced +3V to +5V RS-232 Line Driver/Receiver

VCC = +5V

–10V

VSS Storage Capacitor

VDD Storage Capacitor

–

CHARGE PUMP

The charge pump is a Sipex–patented design

(5,306,954) and uses a unique approach com-

pared to older less–efficient designs. The charge

pump still requires four external capacitors, but

uses a four–phase voltage shifting technique to

attain symmetrical 10V power supplies. There

is a free–running oscillator that controls the four

phases of the voltage shifting. A description of

each phase follows.

Phase 1

— V

SS charge storage —During this phase of

the clock cycle, the positive side of capacitors

1 and C2 are initially charged to +5V. Cl

+ is

then switched to ground and the charge in C

– is

transferred to C

–. Since C

+ is connected to

+5V, the voltage potential across capacitor C

2 is

now 10V.

Phase 2

— V

SS transfer — Phase two of the clock con-

nects the negative terminal of C

2 to the VSS

storage capacitor and the positive terminal of C

to ground, and transfers the generated –l0V to

3. Simultaneously, the positive side of capaci-

tor C

1 is switched to +5V and the negative side

is connected to ground.

Phase 3

— V

DD charge storage — The third phase of the

clock is identical to the first phase — the charge

transferred in C

1 produces –5V in the negative

terminal of C

1, which is applied to the negative

side of capacitor C

2. Since C2

+ is at +5V, the

voltage potential across C

2 is l0V.

Phase 4

— V

DD transfer — The fourth phase of the clock

connects the negative terminal of C

2 to ground,

and transfers the generated l0V across C

2 to C4,

the V

DD storage capacitor. Again, simultaneously

with this, the positive side of capacitor C

1 is

switched to +5V and the negative side is con-

nected to ground, and the cycle begins again.

Since both V+ and V– are separately generated

from V

CC; in a no–load condition V

+ and V– will

be symmetrical. Older charge pump approaches

that generate V– from V+ will show a decrease in

the magnitude of V– compared to V+ due to the

inherent inefficiencies in the design.

The clock rate for the charge pump typically

operates at 15kHz. The external capacitors can

be as low as 0.1

µF with a 16V breakdown

voltage rating.

VCC = +5V

–5V

+5V

VSS Storage Capacitor

VDD Storage Capacitor

–

Figure 1. Charge Pump — Phase 1

Figure 2. Charge Pump — Phase 2

Figure 3. Charge Pump Waveforms

+10V

a) C

GND

b) C

–

–10V

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