Date: 5/25/04

SP6121 Low Voltage, Synchronous Step Down PWM Controller

© Copyright 2004 Sipex Corporation

7

Over Current Protection

Over current protection on the SP6121 is imple-

mented through detection of an excess voltage

condition across the high side PMOS switch

during conduction. This is typically referred to

need of an external sense resistor. The over

current comparator charges an internal sam-

exceeds the 160mV (typ) internal threshold and

the PDRV voltage is low. The discharge/charge

current ratio on the sampling capacitor is about

2%. Therefore, provided that the over current

condition persists, the capacitor voltage will be

pumped up during each time PDRV switches

low. This voltage will trigger an over current

condition upon reaching a CMOS inverter thresh-

old. There are many advantages to this ap-

proach. First, the filtering action of the gated S/

H scheme protects against false and undesirable

triggering that could occur during a minor tran-

sient overload condition or supply line noise.

Furthermore, the total amount of time to trigger

the fault depends on the on-time of the PMOS

switch. Ten, 1

µs pulses are equivalent to twenty,

500ns pulses or one, 10

µs pulse, however, de-

pending on the period, each scenario takes a

different amount of total time to trigger a fault.

Therefore, the fault becomes an indicator of

average power in the PMOS switch.

Although the 160 mV internal threshold is fixed,

source of the PMOS. A 30

µA sink current pro-

grams the additional voltage.

In order for the current limit circuit to operate

must be Kelvin connected to the high side

PMOS’s source and drain pins.

The 160mV threshold and 30

have 3300 ppm/

°C temperature coefficients in

an effort to first order match the thermal charac-

assumed that the SP6121 will be used in com-

pact designs where there is a high amount of

thermal coupling between the PMOS and the

controller.

Output Drivers

The SP6121, unlike some other bipolar control-

ler IC’s, incorporates gate drivers with rail-to-

rail swing that help prevent spurious turn on due

to capacitive coupling. The driver stage consists

of one high side PMOS, 4

Ω driver, PDRV, and

one low side, 4

Ω, NFET driver, NDRV, opti-

mized for driving external power MOSFET’s in

a synchronous buck topology. The output driv-

ers also provide gate drive non-overlap mecha-

nism that provides a dead time between PDRV

and NDRV transitions to avoid potential shoot-

through problems in the external MOSFET’s.

Figure 3 shows typical waveforms for the output

drivers. As with all synchronous designs, care

must be taken to ensure that the MOSFETs are

properly chosen for non-overlap time, enhance-

reverse transfer capacitance Crss, input voltage

and maximum output current.

TIME

NDRV

PDRV

- V(Diode) V

~ 0 V

Voltage

SWN

Voltage

0 V

0 V

Voltage

Vcc-2 V

NON-OVERLAP

2 V

RISE TIME

10 %

90 %

FALL TIME

NDRV(PDRV)

PDRV(NDRV)

5 V

10 %

90 %

5 V

GATE DRIVER TEST CONDITIONS

Figure 3. SP6121 Output Driver Waveforms.

THEORY OF OPERATION: continued