ADVANCED

SP8052

Rev 2.2 (12-04-03)

SP8052 – High Speed 12 Channel PDIC

SIPEX RESERVES THE RIGHT TO MAKE CHANGES TO THIS DATASHEET. CALL FOR UPDATES: 1-978-667-8700.

SIPEX CONFIDENTIAL, ADVANCED & PROPRIETARY. DO NOT DISTRIBUTE OR

COPY

page

PIN ASSIGNMENTS

Pin #

Pin Name

Pin Function

1

Vs

Reference voltage. Bypass to GND with ceramic capacitor 0.1uF

2

GND

Ground pin

3

GK

Output of GK channel (sum of G + K sensor signals)

4

HL

Output of HL channel (sum of H + L sensor signals)

5

EI

Output of EI channel (sum of E + I sensor signals)

6

FJ

Output of FJ channel (sum of F + J sensor signals)

7

WPP1

Output of WPP1 channel (sum of A + B sensor signals)

8

WPP2

Output of WPP2 channel (sum of C + D sensor signals)

9

RF-

Output of RF- channel. RF- = - (A + B +C + D)

10

RF+

Output of RF+ channel. RF+ = A + B + C + D

11

A

Output of A channel

12

B

Output of B channel

13

C

Output of C channel

14

D

Output of D channel

15

GAIN

Logic input of Gain Controller. Allows three states – low, high, and floating - Z

16

Supply voltage. Bypass to GND with ceramic capacitor 0.1uF

BOARD LAYOUT AND GROUNDING

To obtain the best performance from the SP8052, a printed circuit board with ground plane is

required. High quality, low series resistance ceramic 0.1uF bypass capacitors should be used at

the Vcc and Vs pins (pins 1 and 16). These capacitors must be located as close to the pins as

possible. The traces connecting the pins and the bypassing capacitors must be kept short and

should be made as wide as possible.