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PI6C48545 데이터시트(PDF) 2 Page - Pericom Semiconductor Corporation

부품명 PI6C48545
상세설명  3.3V Low Skew 1-to-4 LVTTL/LVCMOS to LVDS Fanout Buffer
PDF  5 Pages
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제조업체  PERICOM [Pericom Semiconductor Corporation]
홈페이지  http://www.pericom.com
Logo PERICOM - Pericom Semiconductor Corporation

PI6C48545 데이터시트(HTML) 2 Page - Pericom Semiconductor Corporation

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PI6C48545
3.3V Low Skew 1-to-4
LVTTL/LVCMOS to LVDS Fanout Buffer
2
PS8770
06/23/05
Pin Description
Name
Pin #
Type
Description
GND
1, 9, 13
P
Connect to Ground
CLK_EN
2
I_PU
Synchronizing clock enable. When high, clock outputs follow clock input. When low, Qx
outputs are forced low, nQx outputs are forced high. LVCMOS/LVTTL level with 80kΩ
pull up.
CLK_SEL
3
I_PD
Clock select input. When high, selects CLK1 input. When low, selects CLK0 input.
LVCMOS/LVTTL level with 80kΩ pull down.
CLK0
4
I_PD
LVCMOS / LVTTL clock input
CLK1
6
I_PD
LVCMOS / LVTTL clock input
NC
5, 7
No internal connection.
OE
8
I_PU
Output Enable. Controls outputs Q0, nQ0 through Q3, nQ3.
VCC
10, 18
P
Connect to 3.3V.
Q3, nQ3
11, 12
O
Differential output pair, LVDS interface level.
Q2, nQ2
14, 15
O
Differential output pair, LVDS interface level.
Q1, nQ1
16, 17
O
Differential output pair, LVDS interface level.
Q0, nQ0
19, 20
O
Differential output pair, LVDS interface level.
Notes:
1. I = Input, O = Output, P = Power supply connection, I_PD = Input with pull down, I_PU = Input with pull up.
Pin Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
CIN
Input Capacitance
6
pF
R_pullup
Input Pullup Resistance
80
kΩ
R_pulldown
Input Pulldown Resistance
80
Control Input Function Table
Inputs
Outputs
OE
CLK_EN
CLK_SEL
Selected Source
Q0:Q3
nQ0:nQ3
1
0
0
CLK0
Diasbled: Low
Diasbled: High
1
0
1
CLK1
Disabled: Low
Disabled: High
1
1
0
CLK0
Enabled
Enabled
1
1
1
CLK1
Enabled
Enabled
0
x
x
HiZ
HiZ
Notes:
1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show below.



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