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PI6CFGL601B 데이터시트(PDF) 8 Page - Pericom Semiconductor Corporation |
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PI6CFGL601B 데이터시트(HTML) 8 Page - Pericom Semiconductor Corporation |
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8 / 13 page ![]() 8 PI6CFGL601B RevA 01/16/15 PI6CFGL601B 6-Output Low Power PCIE Gen 1-2-3 Clock Generator All trademarks are property of their respective owners. Supply Voltage to Ground Potential......................................................4.6V All Inputs and Output...................................................-0.5V to VDD +0.5V Ambient Operating Temperature.......................................-40°C to +85oC Storage Temperature.......................................................... –65°C to +150°C Juction Temperature ............................................................................ 125°C Soldering Temperature.........................................................................260°C ESD Protection (Input) ......................................................... 2000V (HBM) Note: Stresses greater than those listed under MAXIMUM RAT- INGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Electrical Characteristics–Current Consumption T A = -40~85 o C; Supply Voltage VDD = 3.3 V +/-10%; VDDO = 1.8V +/-10%, See Test Loads for loading conditions Symbol Parameters Condition Min. Typ. Max. Units I DD3.3 Operating Supply Current1 VDD, All outputs active @100MHz 50 65 mA Notes: 1. Guaranteed by design and characterization, not 100% tested in production. Electrical Characteristics–Output Duty Cycle, Jitter, and Skew Characteristics T A = -40~85 o C; Supply Voltage VDD = 3.3 V +/-10%; VDDO = 1.8V +/-10%, See Test Loads for Loading Conditions Symbol Parameters Condition Min. Typ. Max. Units t DC Duty Cycle1 Measured differentially, PLL Mode 45 55 % tskew Skew, Output to Output1 VT = 50% 50 ps t jcyc-cyc Jitter, Cycle to cycle1,2 PLL mode 50 ps Notes: 1. Guaranteed by design and characterization, not 100% tested in production. 2. Measured from differential waveform Electrical Characteristics–Input/Supply/Common Output Parameters T A = -40~85 o C; Supply Voltage VDD = 3.3 V +/-10%; VDDO = 1.8V +/-10% Symbol Parameters Condition Min. Typ. Max. Units V DD Supply Voltage1 Supply voltage for core, analog 3.0 3.3 3.6 V V DDO Supply Voltage1 Supply voltage outputs 1.65 1.8 2.0 V V IH Input High Voltage1 Single-ended inputs, except SMBus 0.65 V DD V DD +0.3 V V IL Input Low Voltage1 Single-ended inputs, except SMBus -0.3 0.35 V DD V V OH Output High Voltage1 Single-ended outputs, except SMBus. I OH = -2mA V DD -0.45 V V OL Outputt Low Voltage1 Single-ended outputs, except SMBus. I OL = -2mA 0.45 V 15-0018 |
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