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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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IS25LP032 데이터시트(PDF) 40 Page - Integrated Silicon Solution, Inc |
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IS25LP032 데이터시트(HTML) 40 Page - Integrated Silicon Solution, Inc |
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40 / 90 page  IS25LP032/064/128 Integrated Silicon Solution, Inc.- www.issi.com 40 Rev. D 10/03/2014 8.12 CHIP ERASE OPERATION (CER, C7h/60h) A Chip Erase (CER) instruction erases the entire memory array of a IS25LP032/064/128. Before the execution of CER instruction, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is automatically reset after completion of a chip erase operation. The CER instruction code is input via the SI. Erase operation will start immediately after CE# is pulled high, otherwise the CER instruction will not be executed. The internal control logic automatically handles the erase voltage and timing. Refer to Figure 8.18-8.19 for the Chip Erase Sequence. Figure 8.18 Chip Erase Sequence Instruction = C7h/60h CE# SCK SIO 0 1 2 3 4 5 6 7 Mode 3 Mode 0 SO High Impedance Figure 8.19 Chip Erase Sequence (QPI) C7h/60h CE# SCK IO[3:0] 0 1 Mode 3 Mode 0 |
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