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2016-01-0001

PT0579

01/27/16

5

PI4GTL2002

2-bit bidirectional low voltage translator

Figure.2 Load Circuit for Outputs

Application Information

For the bidirectional clamping configuration, higher voltage to lower voltage or lower voltage to higher voltage, the GREF

input must be connected to DREF and both pins pulled to HIGH side VCC through a pull-up resistor (typically 200 kΩ). A filter

capacitor on DREF is recommended. The processor output can be totem pole or open-drain (pull-up resistors may be required) and

the chip set output can be totem pole or open-drain (pull-up resistors are required to pull the Dn outputs to VCC). However, if

either output is totem pole, data must be unidirectional or the outputs must be 3-stateable and the outputs must be controlled by

some direction control mechanism to prevent HIGH-to-LOW contentions in either direction. If both outputs are open-drain, no

direction control is needed. The opposite side of the reference transistor (SREF) is connected to the processor core power supply

voltage. When DREF is connected through a 200 kΩ resistor to a 3.3 V to 5.5 V VCC supply and SREF is set between 0.8 V to

(VCC -1.5 V), the output of each Sn has a maximum output voltage equal to SREF and the output of each Dn has a maximum

output voltage equal to VCC.