ADC12D040EVAL datasheet(4/22 Pages) NSC

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Pin Descriptions and Equivalent Circuits

Pin No.

Symbol

Equivalent Circuit

Description

ANALOG I/O

INA+

INB+

Non-Inverting analog signal Inputs. With a 2.0V reference

voltage each input signal level is 2.0 V

P-P centered on VCM.

INA−

INB−

Inverting analog signal Input. With a 2.0V reference voltage

the input signal level is from 2.0 V

P-P centered on VCM. This

pin may be connected to V

CM for single-ended operation, but

a differential input signal is required for best performance.

REF

Reference input. This pin should be bypassed to AGND with

a 0.1 µF monolithic capacitor. V

REF is 2.0V nominal and

should be between 1.0V to 2.4V.

INT/EXT REF

REF select pin. With a logic low at this pin the internal 2.0V

reference is selected. With a logic high on this pin an external

reference voltage should be applied to V

REF input pin 7.

RPA

RPB

These pins are high impedance reference bypass pins only.

Connect a 0.1 µF capacitor from each of these pins to AGND.

DO NOT connect anything else to these pins.

RNA

RNB

RMA

RMB

DIGITAL I/O

CLK

Digital clock input. The range of frequencies for this input is

100 kHz to 50 MHz (typical) with guaranteed performance at

40 MHz. The input is sampled on the rising edge of this input.

OEA

OEB

OEA and OEB are the output enable pins that, when low,

enables their respective TRI-STATE data output pins. When

either of these pins is high, the corresponding outputs are in a

high impedance state.

PD is the Power Down input pin. When high, this input puts

the converter into the power down mode. When this pin is

low, the converter is in the active mode.

Output Format pin. A logic low on this pin causes output data

to be in straight binary. A logic high on this pin causes the

output data to be in 2’s complement format.

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