MB91F528 datasheet(6/241 Pages) SPANSION

6 / 241 page

D a t a S h e e t

March 28, 2014, MB91F528_DS705-00016-1v0-E

CONFIDENTIAL

 Built-in RAM capacity

 Main RAM

MB91F527 : 192KB

MB91F528 : 192KB + 128KB (128KB located in the AHB area, a penalty given at access)

 Backup RAM 16KB

 General-purpose ports :

MB91F527R/MB91F528R :

115 (none sub oscillation), 113 (with sub oscillation)

MB91F527U/MB91F528U :

147 (none sub oscillation), 145 (with sub oscillation)

MB91F527M/MB91F528M :

177 (none sub oscillation), 175 (with sub oscillation)

MB91F527Y/MB91F528Y

219 (none sub oscillation), 217 (with sub oscillation)

Included I

2C pseudo open drain ports : Max. 30

 External bus interface

 22-bit address, 8/16-bit data

 DMA Controller

 Up to 16 channels can be started simultaneously.

 2 transfer factors (Internal peripheral request and software)

 A/D converter (successive approximation type)

 12-bit resolution : Max. 64 channels (32 channels +32 channels)

 Conversion time : 1μs

 D/A converter (R-2R type)

 8-bit resolution : 2 channels

 External interrupt input: Max. 24 channels

 Level ("H" / "L"), or edge detection (rising or falling) supported

 Multi-function serial communication (built-in transmission/reception FIFO memory) : Max. 20 channels

5V tolerant input 8 channels (ch.6, ch.8, ch.9, ch.11, ch.16 to ch.19) CMOS hysteresis input

< UART (Asynchronous serial interface) >

 Full-duplex double buffering system, 64-byte transmission FIFO memory, 64-byte reception FIFO

memory

 Parity or no parity is selectable.

 Built-in dedicated baud rate generator

 The external clock can be used as the transfer clock

 Parity, frame, and overrun error detect functions provided

 DMA transfer support

 Full-duplex double buffering system, 64-byte transmission FIFO, memory, 64-byte reception FIFO

memory

 SPI supported; master and slave systems supported; 5-bit to 16-bit, 20-bit, 24-bit, 32-bit data length

can be set.

 Built-in dedicated baud rate generator (Master operation)

 The external clock can be entered. (Slave operation)

 Overrun error detection function is provided

 DMA transfer support

 Serial chip select SPI function

 Full-duplex double buffering system, 64-byte transmission FIFO memory, 64-byte reception FIFO

memory

 LIN protocol revision 2.1 supported

 Master and slave systems supported

 Framing error and overrun error detection

 LIN synch break generation and detection; LIN synch delimiter generation

 Built-in dedicated baud rate generator

 The external clock can be adjusted by the reload counter

 DMA transfer support

 Hardware assist function

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