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MB91F587LD 데이터시트(PDF) 155 Page - SPANSION

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152
MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
(11) External bus I/F (synchronous mode) timing
(TA: Recommended operating conditions, VCC =AVCC=5.0V±10%, VSS=AVSS=0.0V)
(External load capacitance 50pF)
Parameter
Symbol
Pin name
Value
Unit
Remarks
Min
Max
Cycle time
tCYC
SYSCLK
25
-
ns
ASX delay time
tCHASL,
tCHASH
SYSCLK,
ASX
0.5
18.0
ns
CS0X to CS3X
delay time
tCHCSL,
tCHCSH
SYSCLK,
CS0X to CS3X
0.5
18.0
ns
A00 to A21
delay time
tCHAV,
tCHAX
SYSCLK,
A00 to A21
0.5
18.0
ns
RDX delay time
tCHRL,
tCHRH
SYSCLK,
RDX
0.5
18.0
ns
RDX minimum pulse
tRLRH
RDX
tCYC ×
2 - 20
-
ns RWT=1, set RWT to 1 or
more. *
Data setup → RDX ↑
time
tDSRH
RDX,
D16 to D31
18 + tCYC
-
ns RWT=1, set RWT to 1 or
more. *
RDX ↑ → data hold
tRHDH
0
-
ns
WRnX delay time
tCHWL,
tCHWH
SYSCLK,
WR0X, WR1X
0.5
18.0
ns
WRnX
minimum pulse width
tWLWH
WR0X, WR1X tCYC - 10
-
ns WWT=0*
SYSCLK ↑ →
data output time
tCHDV
SYSCLK,
D16 to D31
0.5
18.0
ns
SYSCLK ↑ →
data hold time
tCHDX
-
18
ns Set WRCS to 1 or more.
SYSCLK ↑ →
address output time
tCHMAV
SYSCLK,
D16 to D31
0.5
18.0
ns
SYSCLK ↑ →
address hold time
tCHMAX
-
18
ns
In multiplex mode, set as
follows:
•
Set CSWR and CSRD to 2
or more.
•
Set to ADCY>ASCY.
To prevent protocol
violation, satisfy the
following conditions:
ADCY + 1 ≤ ACS + CSRD
ADCY + 1 ≤ ACS + CSWR
ASCY + 1 ≤ ACS + CSRD
ASCY + 1 ≤ ACS + CSWR
For details, see Hardware
Manual.
*: If the bus is expanded by automatic wait insertion or RDY input, add time (tCYC × the number of expanded
cycles) to the rated value.



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