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MB91F587LD 데이터시트(PDF) 158 Page - SPANSION

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D at aS h ee t
August 22, 2014, MB91F587LA_DS705-00012-2v0-E
155
CONFIDENTIAL
(12) External bus I/F (Asynchronous mode) timing
(TA: Recommended operating conditions, VCC = AVCC=5.0V±10%, VSS=AVSS=0.0V)
(External load capacitance 50pF)
Parameter
Symbol
Pin
name
Value
Unit
Remarks
Min
Max
Cycle time
tCYC
SYSCLK
25
-
ns
Address setup →
RDX ↑ time
tASRH
RDX,
A00 to
A21
2 × tCYC – 12 2 × tCYC + 12
ns RWT=1, set RWT to 1 or
more.*
RDX ↑ →
Address hold
tRHAH
tCYC – 12
tCYC + 12
ns Set RDCS to 1 or more.
Data setup
→
RDX ↑ time
tDSRH
RDX,
D16 to
D31
18 +tCYC
-
ns RWT=1, set RWT to 1 or
more.
RDX ↑ →
Data hold
tRHDH
0
-
ns
Address setup →
WRnX ↑ time
tASWH
WR0X to
WR1X,
A00 to
A21
tCYC – 12
tCYC + 12
ns WWT=0.
*
WRnX ↑ →
Address hold
tWHAH
tCYC – 12
tCYC + 12
ns Set WRCS to 1 or more.
Data setup
→
WRnX ↑ time
tDSWH
WR0X to
WR1X,
D16 to
D31
tCYC – 16
tCYC + 16
ns WWT=0.
*
WRnX ↑ →
Data hold
tWHDH
tCYC – 16
tCYC + 16
ns Set WRCS to 1 or more.
Address setup →
ASX ↑ time
tMASASH
ASX,
D16 to
D31
tCYC – 16
tCYC + 16
ns ASCY=0.
ASX ↑ →
Address hold
tMASHAH
tCYC – 16
tCYC + 16
ns
In multiplex mode, set as
follows:
•
Set CSWR and CSRD to 2
or more.
•
Set to ADCY>ASCY.
To prevent protocol
violation, satisfy the
following conditions:
ADCY + 1 ≤ ACS + CSRD
ADCY + 1 ≤ ACS + CSWR
ASCY + 1 ≤ ACS + CSRD
ASCY + 1 ≤ ACS + CSWR
For details, see Hardware
Manual.
*: If the bus is expanded by automatic wait insertion or RDY input, add time (tCYC × the number of expanded
cycles) to the rated value.



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