MCP6N16 datasheet(39/58 Pages) MICROCHIP

39 / 58 page

 2014 Microchip Technology Inc.

DS20005318A-page 39

MCP6N16

4.1.5

NOISE PERFORMANCE

As shown in Figure 2-73, the noise density is white at

low frequencies; the 1/f noise is negligible for almost all

applications. As a result, the time domain data in

Figures 2-77, 2-78 and 2-79 is well behaved.

4.2

Overview of Zero-Drift Operation

Figure 4-4 shows a simplified diagram of the MCP6N16

zero-drift INAs. This diagram will be used to explain

how low voltage errors are reduced in this architecture

(much better VOS, TC1 (∆VOS/∆TA), CMRR, CMRR2,

PSRR, AOL and 1/f noise).

FIGURE 4-4:

Simplified Zero-Drift INA Functional Diagram.

4.2.1

BUILDING BLOCKS

The Main Amplifiers (GM1 and GM2) are designed for

high gain and bandwidth, with a differential topology.

The main input pairs (+ and - pins at the top left) are for

the higher frequency portion of the input signal. The

auxiliary input pair (+ and - pins at the bottom left of

GM1) is for the low frequency portion of the input signal

and corrects the INA’s input offset voltage. Both inputs

are added together internally.

The Auxiliary Amplifiers (GA1 and GA2), the Chopper

Input Switches and the Chopper Output Switches

provide a high DC gain to the input signal. DC errors

are modulated to higher frequencies and white noise to

low frequencies.

The Low-Pass Filter reduces high-frequency content,

including harmonics of the Chopping Clock.

The Output Buffer (RM4) converts current to voltage

and drives external loads at the VOUT pin.

The Oscillator runs at fCLK = 200 kHz. Its output is

divided by 8, to produce the Chopping Clock rate of

fCHOP =25 kHz.

The internal POR part starts the part in a known good

state, protecting against power supply brown-outs. The

Digital Control block outputs clocks and POR events.

4.2.2

CHOPPING ACTION

Figure 4-5 shows the amplifier connections for the first

phase of the Chopping Clock and Figure 4-6 shows

them for the second phase. The slow voltage errors

alternate in polarity, making the average error small.

FIGURE 4-5:

First Chopping Clock Phase;

Simplified Diagram.

VIP

VIM

GM1

VOUT

RM4

GA1

Chopper

Input

Switches

Chopper

Output

Switches

Oscillator

Low-Pass

Filter

Digital Control

VFG

VREF

GA2

Chopper

Input

Switches

POR

GM2

VIP

VIM

GA1

VFG

VREF

GA2

Low-Pass

Filter

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