Micro Crystal

Real Time Clock / Calendar Module

RV-8564

20/40

9.4. ALARM FLAG

By clearing the MSB of one or more of the alarm registers AE_x (Alarm Enable), the corresponding alarm

condition(s) are active. When an alarm occurs, AF is set to logic 1. The asserted AF can be used to generate an

interrupt ( INT ). The AF is cleared using the interface.

The registers at addresses 09h through 0Ch contain alarm information. When one or more of these registers is

loaded with a valid minute, hour, day or weekday and its corresponding Alarm Enable bit (AE_x) is logic 0, then that

information is compared with the current minute, hour, day and weekday. When all enabled comparisons first

match, the Alarm Flag (AF in register Control / Status 2) is set to logic 1.

The generation of interrupts from the alarm function is controlled via bit AIE. If bit AIE is enabled, the INT pin

follows the condition of bit AF. AF will remain set until cleared by the interface. Once AF has been cleared it will

only be set again when the time increments to match the alarm condition once more. Alarm registers which have

their AE_x bit at logic 1 are ignored.