| 전자부품 데이터시트 검색엔진 |
|
AD7779 데이터시트(PDF) 4 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD7779 데이터시트(HTML) 4 Page - Analog Devices |
|
4 / 97 page ![]() AD7779 Data Sheet Rev. 0 | Page 4 of 97 FUNCTIONAL BLOCK DIAGRAM AVDD1x REF_OUT REFx+ VCM AVDD2 AVSSx AVDD4 CONVST_SAR IOVDD AREGxCAP DREGCAP CLOCK MANAGER XTAL1 XTAL2/MCLK SYNC_IN SYNC_OUT START REFx– DCLK DRDY DOUT3 DOUT2 DOUT1 DOUT0 FORMAT1 FORMAT0 MODE3/ALERT MODE2/GPIO2 MODE1/GPIO1 MODE0/GPIO0 ALERT/CS DCLK2/SCLK DCLK1/SDI DCLK0/SDO RESET Σ-∆ ADC AIN0+ AIN0– 280mV p-p Σ-∆ ADC REFERENCES EXT_REF INT_REF AIN1+ AIN1– Σ-∆ ADC REFERENCES AIN2+ AIN2– Σ-∆ ADC REFERENCES AIN3+ AIN3– Σ-∆ ADC REFERENCES AIN4+ AIN4– Σ-∆ ADC REFERENCES AIN5+ AIN5– REFERENCES AIN6+ AIN6– REFERENCES DIAGNOSTIC INPUTS AIN7+ AIN7– SINC3/ SRC FILTER GAIN OFFSET COMMON- MODE VOLTAGE ANALOG LDO 2.5V REF SINC3/ SRC FILTER GAIN OFFSET SINC3/ SRC FILTER GAIN OFFSET SINC3/ SRC FILTER GAIN OFFSET SINC3/ SRC FILTER GAIN OFFSET SINC3/ SRC FILTER GAIN OFFSET SINC3/ SRC FILTER GAIN OFFSET SINC3/ SRC FILTER GAIN OFFSET Σ-∆ ADC Σ-∆ ADC AUXAIN+ AUXAIN– DATA OUTPUT INTERFACE REGISTER MAP AND LOGIC CONTROL HARDWARE MODE CONFIGURATION SPI INTERFACE AD7779 SAR ADC DIGITAL LDO PGA PGA PGA PGA PGA PGA PGA PGA Figure 1. |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |