ADAV4601 datasheet(47/60 Pages) AD

47 / 60 page

ADAV4601

Rev. B | Page 47 of 60

Address 0x0126 SRC Delay Register (Default: 0x0000)

This register is used to set the delay for the SRC channel.

Table 43.

Bit No.

Bit Name

Description

Default

Bits[15:12]

Reserved

Always write as 0 if writing to this register.

0000

Bits[11:0]

SRC delay

The range of values is 20.83 μs to 42 ms in 20.83 μs (1 sample delay) steps.

000000000000

0x000 = 20.83 μs (1 sample delay)

0x001 = 41.66 μs (2 sample delay)

...

0x7E1 = 42 ms (2017 sample delay)

Address 0x0127 SRC Control Register (Default: 0x0030)

This register is used to enable the DSP mute circuit for SRC1 and SRC2. If SRC is enabled and detects an error, it will mute the output of

the SRC. It also bypasses the de-emphasis filters of the SRC.

Table 44.

Bit No.

Bit Name

Description

Default

Bits[15:6]

Reserved

Always write as 0 if writing to this register.

0000000000

Bit[5]

SRC1 de-emphasis filter bypass

This bypasses the SRC1 de-emphasis filter.

0b = bypass

1b = enabled

Bit[4]

SRC2 de-emphasis filter bypass

This bypasses the SRC2 de-emphasis filter.

0b = bypass

1b = enabled

Bit[3]

SRC1 DSP mute circuit bypass

If an error is detected, it mutes the output of SRC1.

0b = enabled

1b = disabled

Bit[2]

SRC2 Channel A DSP mute circuit bypass

If an error is detected, it mutes the output of SRC2.

0b = enabled

1b = disabled

Bit[1]

SRC2 Channel B DSP mute circuit bypass

If an error is detected, it mutes the output of SRC2.

0b = enabled

1b = disabled

Bit[0]

SRC2 Channel C DSP mute circuit bypass

If an error is detected, it mutes the output of SRC2.

0b = enabled

1b = disabled

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