ADAV4601BSTZ datasheet(40/60 Pages) AD

40 / 60 page

ADAV4601

Rev. B | Page 40 of 60

Address 0x0112 and Address 0x0113 Woofer Right Balance Control Registers (Default: 0x0080, 0x0000)

These two registers control the balance for the right tweeter output.

The balance control words are 28-bit words in twos complement and a 5.23 format. This means there are five bits to the left of the decimal

point of which the most significant bit is the sign bit.

Table 30.

Bit No.

Bit Name

Description

Default

Bits[15:12]

Reserved

Always write as 0 if writing to this register.

0000

Bits[11:0]

Woofer right balance control register[27:0]

0x0112 Bits[11:0] = woofer right balance control register[27:16]

000010000000

Bits[15:0]

Woofer right balance control register[27:0]

0x0113 Bits[15:0] = woofer right balance control register[15:0]

0000000000000000

Address 0x0114 and Address 0x0115 Main Volume Control Registers (Default: 0x0080, 0x0000)

These two registers control the volume for the main channel output.

The volume control words are 28-bit words in twos complement and a 5.23 format. This means there are five bits to the left of the decimal

point of which the most significant bit is the sign bit.

Table 31.

Bit No.

Bit Name

Description

Default

Bits[15:12]

Reserved

Always write as 0 if writing to this register.

0000

Bits[11:0]

Woofer right balance control register[27:0]

0x0114 Bits[11:0] = main volume Bits[27:16]

000010000000

Bits[15:0]

Woofer right balance control register[27:0]

0x0115 Bits[15:0] = main volume Bits[15:0]

0000000000000000

Address 0x0116 Tweeter Peak Limiter Control Register (Default: 0x0F00)

This register controls the peak limiter for the main output tweeter.

Table 32.

Bit No.

Bit Name

Description

Default

Bits[15:13]

Reserved

Always write as 0 if writing to this register.

000

Bits[12:8]

Post gain

These register bits control the post gain in the range of +15 dB to −15 dB in +1 dB steps.

01111

0x00 = +15 dB

0x01 = +14 dB

…

0x08 = +7 dB

…

0x0F = +0 dB

…

0x16 = −7 dB

…

0x1D = −14 dB

0x1E = −15 dB

Bits[7:5]

Hold time

These register bits control the hold time for the limiter, which is the time in ms that the limiter

holds the attenuated level after the current input to the limiter function falls below the limiter

threshold.

000

0x0 = 0 ms

0x1 = 10 ms

0x2 = 20 ms

0x3 = 30 ms

0x4 = 40 ms

0x5 = 50 ms

0x6 = 60 ms

0x7 = 70 ms

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