Connection Diagram

Pin Descriptions

Name

Pin No.

Description

EAV

1

End of active video flag. For component video, a logic low is output for one cycle of the

parallel clock every time an EAV timing reference is detected. The pulse is aligned with the

fourth word of the timing reference (the XYZ word). For composite video, this line is always

asserted high.

V

EE

2, 4, 26

Negative supply pins.

NC

3

Unused pin.

SDI+, SDI−

5, 6

Differential serial data inputs.

SCI+, SCI−

7, 8

Differential serial clock inputs.

NRZI

9

A logic high at this pin enables NRZI-to-NRZ conversion.

DESC

10

A logic high at this pin enables descrambling.

FE

11

Frame enable. Enables resynchronization of the parallel word at the next TRS.

V

CC

12

Positive supply pin.

VCP

13

Parallel clock high level programming pin. The voltage at this supply pin defines the logic high

level for the parallel clock output.

NSP

14

New sync position. Indicates that the most recent TRS is in a new position relative to the

previous TRS. Remains high until the parallel rate clock is aligned properly with the TRS.

TRS

15

Timing reference flag. A logic low is output for the duration of the TRS.

PCLK

16

Parallel clock output. The rising edge of this clock is located at the center of the parallel data

window.

PD0–9

17,

19–25,

27, 28

Parallel data outputs.

VDP

18

Parallel data high level programming pin. The voltage at this supply pin defines the logic high

level for the data outputs.

DS100086-2

28-Pin PLCC

Order Number CLC011ACQ, or CLC011BCQ

See NS Package Number V28A

www.national.com

2