| 전자부품 데이터시트 검색엔진 |
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DS2143 데이터시트(PDF) 13 Page - Dallas Semiconductor |
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DS2143 데이터시트(HTML) 13 Page - Dallas Semiconductor |
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13 / 44 page ![]() DS2143/DS2143Q 13 of 44 CCR: COMMON CONTROL REGISTER (Address=14 Hex) (MSB) (LSB) LLB THDB3 TG802 TCRC4 RSM RHDB3 RG802 RCRC4 SYMBOL POSITION NAME AND DESCRIPTION LLB CCR.7 Local Loopback. 0 = loopback disabled. 1 = loopback enabled. THDB3 CCR.6 Transmit HDB3 Enable. 0 = HDB3 disabled. 1 = HDB3 enabled. TG802 CCR.5 Transmit G.802 Enable. See Section 13 for details. 0 = do not force TCHBLK high during bit 1 of timeslot 26. 1 = force TCHBLK high during bit 1 of timeslot 26. TCRC4 CCR.4 Transmit CRC4 Enable. 0 = CRC4 disabled. 1 = CRC4 enabled. RSM CCR.3 Receive Signaling Mode Select. 0 = CAS signaling mode. 1 = CCS signaling mode. RHDB3 CCR.2 Receive HDB3 Enable. 0 = HDB3 disabled. 1 = HDB3 enabled. RG802 CCR.1 Receive G.802 Enable. See Section 13 for details. 0 = do not force RCHBLK high during bit 1 of timeslot 26 1 = force RCHBLK high during bit 1 of timeslot 26. RCRC4 CCR.0 Receive CRC4 Enable. 0 = CRC4 disabled. 1 = CRC4 enabled. LOCAL LOOPBACK When CCR.7 is set to a 1, the DS2143 will enter a Local LoopBack (LLB) mode. This loopback is useful in testing and debugging applications. In LLB, the DS2143 will loop data from the transmit side back to the receive side. This loopback is synonymous with replacing the RCLK input with the TCLK signal, and the RPOS/RNEG inputs with the TPOS/TNEG outputs. When LLB is enabled, the following will occur: 1. data at RPOS and RNEG will be ignored; 2. all receive side signals will take on timing synchronous with TCLK instead of RCLK; 3. all functions are available. |
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