Address/data waveform

Each programmable address/data pin can be externally set to one of the following three logic states:

The ²Open² state data input is interpreted as logic low by the decoders since the decoder output only

have two states.

Address/data programming (preset)

The status of each address/data pin can be individually preset to logic ²high², ²low²,or ²floating².Ifa

transmission enable signal is applied, the encoder scans and transmits the status of the 18 bits of ad-

dress/data serially in the order A0 to AD17 for the HT600/HT640/HT680 and A0 to D17 for the

HT6187/HT6207/HT6247.

There are some packaging limitations. The 18-pin DIP HT680, for example, offers four external data

bits and eight external address bits. The remaining unpackaged bits or dummy codes are treated as

floating for A0~AD17 or as pull-low for D12~D17. During an information transmission these bits are

still located in their original position. But if the trigger signal is not applied, the chip only consumes a

standby current which is less than 1mA.

The address pins are usually preset to transmit data codes with particular security codes by the DIP

switches or PCB wiring, while the data is selected using push buttons or electronic switches.

The following figure shows an application using the HT680:

6

July 8, 1999

V S S A 0A 1A 2A 3A 6A 7A 8A 9

VD D T E A D 11 A D 12 A D 14 A D 15

OS C 1

OS C 2

DO UT

T r ans m i s s i on

m edi um

VD D

"O n e "

" Z er o"

" O p en"

A ddr es s / D a t a B i t

f o sc ¸ 33

Address/Data bit waveform