Closed Loop Gain Selection

The CLC407 is a current feedback op amp with

three closed loop gains without using any external gain or

feedback resistors.

Implement gains of +2, +1, and

-1V/V by connecting pins 2 and 3 as described in the

chart below.

The gain accuracy of the CLC407 is excellent and

stable over temperature change.

The internal gain

with a process variation of ± 20% and a temperature

coefficient of ˜ 2000ppm/°C. Although their absolute

values change with processing and temperature, their

will suffer .

Achieve a gain of +1V/V by removing all resistive and

capacitive connections between pin 2 and ground plane.

Any capacitive coupling between pin 2 and ground will

cause high frequency peaking in the frequency domain

response and overshoot in the time domain response.

Minimize this capacitive coupling during layout by removing

ground plane near pins 1, 2, and 3. This minimization

should produce a response similar to the plot labeled

“open” in Graph 1. If desired flatness is greater than plot

“open” in Graph 1, two options remain to further flatten

the frequency response. First, try shorting the inverting

input (pin 2) to the non-inverting input (pin 3).

This

response is labeled “short” in Graph 1.

Next, try

inserting a 300

Ω resistor R between the non-inverting

input (pin 2) as shown in Figure 1.

This response is

labeled “300

Ω ” in Graph 1. Notice an “open” produces a

response with obvious peaking and maximum bandwidth,

a “short” minimizes peaking and bandwidth, and finally

300

Ω slightly extends bandwidth with minimal peaking.

Graph 1

Gain

Input Connections

Acl

Non-Inverting (pin3)

Inverting (pin2)

-1V/V

ground

input signal

+1V/V

input signal

NC (open)

+2V/V

input signal

ground

-60

-20

140

4.0

3.0

2.0

1.0

0

-1.0

1.0

0

-1.0

-2.0

-3.0

-4.0

20

60

100

CLC407 OPERATION

Small Signal Pulse Response

Time (5ns/div)

0.20

0.10

-0.10

-0.20

0.00

Large Signal Pulse Response

Time (5ns/div)

2.0

1.0

-1.0

-2.0

0.0

Settling Time vs. Capacitive Load

10

100

1000

1k

+

-

250

Ω

250

Ω

V

CLC407

50

40

30

20

10

0

100

80

60

40

20

0

Short Term Settling Time

Time (ns)

0.2

0.1

-0.1

-0.2

0.0

020

100

80

60

40

PSRR and CMRR

10k

100k

1M

Frequency (Hz)

10M

100M

60

50

40

30

20

10

PSRR

CMRR

Frequency Response vs.

Unity Gain Configuration

Frequency (MHz)

1

10

100

Short

300

Ω

Open

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