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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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CTL0353PS-R3 데이터시트(PDF) 1 Page - CT Micro International Corporation |
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CTL0353PS-R3 데이터시트(HTML) 1 Page - CT Micro International Corporation |
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1 / 11 page  CT Micro Rev 1 Proprietary & Confidential Page 1 Nov, 2013 CTL0353PS-R3 P-Channel Enhancement MOSFET Package Outline Schematic Features Drain-Source Breakdown Voltage VDSS -30 V Drain-Source On-Resistance RDS(ON) 58m , at V GS = -10V, ID= -3.2A RDS(ON) 75m , at V GS = -4.5V, ID= -2.5A Continuous Drain Current at TC=25℃ ID = -3.0A Advanced high cell density Trench Technology RoHS Compliance & Halogen Free Applications Power Management Lithium Ion Battery Description The CTL0353PS-R3 is the P-Channel logic enhancement mode power field effect transistors are produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular phone and notebook computer power management and other battery powered circuits where low in-line power loss are needed in a very small outline surface mount package. Gate Source Drain Gate Drain Source |
유사한 부품 번호 - CTL0353PS-R3 |
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유사한 설명 - CTL0353PS-R3 |
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