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CY7C64013
CY7C64113
Document #: 38-08001 Rev. **
Page 43 of 48
Notes:
9.
Per Table 7-6 of revision 1.1 of USB specification.
10. For 25-pF load.
11. Assumes chip select CS is asserted (LOW).
23.0
Switching Characteristics (fOSC = 6.0 MHz)
Parameter
Description
Min.
Max.
Unit
Clock Source
fOSC
Clock Rate
6 ±0.25%
MHz
tcyc
Clock Period
166.25
167.08
ns
tCH
Clock HIGH time
0.45 tCYC
ns
tCL
Clock LOW time
0.45 tCYC
ns
USB Full Speed Signaling[9]
trfs
Transition Rise Time
4
20
ns
tffs
Transition Fall Time
4
20
ns
trfmfs
Rise / Fall Time Matching; (tr/tf)
90
111
%
tdratefs
Full Speed Date Rate
12 ±0.25%
Mb/s
DAC Interface
tsink
Current Sink Response Time
0.8
µs
HAPI Read Cycle Timing
tRD
Read Pulse Width
15
ns
tOED
OE LOW to Data Valid[10, 11]
40
ns
tOEZ
OE HIGH to Data High-Z[11]
20
ns
tOEDR
OE LOW to Data_Ready Deasserted[10, 11]
0
60
ns
HAPI Write Cycle Timing
tWR
Write Strobe Width
15
ns
tDSTB
Data Valid to STB HIGH (Data Set-up Time)[11]
5
ns
tSTBZ
STB HIGH to Data High-Z (Data Hold Time)[11]
15
ns
tSTBLE
STB LOW to Latch_Empty Deasserted[10, 11]
0
50
ns
Timer Signals
twatch
Watch Dog Timer Period
8.192
14.336
ms
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