CLC5633IM datasheet(13/17 Pages) NSC

13 / 17 page

Application Division (Continued)

The input is AC coupled to prevent the need for level shifting

the input signal at the source. The resistive voltage divider

biases the non-inverting input to V

CC ÷ 2 = 2.5V (For VCC =

+5V).

Dual Supply Operation

The CLC5633 operates on dual supplies as well as signal

supplies. The non-inverting and inverting configurations are

shown in

Figure 7, Figure 8, and Figure 9.

Load Termination

The CLC5633 can source and sink near equal amounts of

current. For optimum performance, the load should be tied to

CM.

CLC5633

0.1

µF

6.8

µF

VCC

Note: Channel 2 and 3 not shown.

Ω

2.5

Low frequency cutoff

2R C

g C

=−

where Rg = 1kΩ.

Vin

VCC

DS015005-42

FIGURE 4. AC Coupled, A

V = −1V/V Configuration

CLC5633

0.1

µF

6.8

µF

VCC

Note: Channel 2 and 3 not shown.

Ω

Vin

VCC

2.5

Low frequency cutoff

2R C

where R

in C

source

=>>

DS015005-43

FIGURE 5. AC Coupled, A

V = +1V/V Configuration

CLC5633

0.1

µF

6.8

µF

VCC

Note: Channel 2 and 3 not shown.

Ω

Vin

VCC

2.5

Low frequency cutoff

2R C

where R

in C

source

=>>

DS015005-44

FIGURE 6. AC Coupled, A

V = +2V/V Configuration

CLC5633

0.1

µF

6.8

µF

VCC

Ω

Vin

Note: Rb provides DC bias for the

non-inverting input. Select Rt to

yield desired Rin = Rt||1kΩ.

Channel 2 and 3 not shown.

6.8

µF

0.1

µF

VEE

DS015005-45

FIGURE 7. Dual Supply, A

V = −1V/V Configuration

CLC5633

0.1

µF

6.8

µF

VCC

Ω

Vin

Note: Channel 2 and 3 not shown.

6.8

µF

0.1

µF

VEE

DS015005-46

FIGURE 8. Dual Supply, A

V = +1V/V Configuration

CLC5633

0.1

µF

6.8

µF

VCC

Ω

Vin

Note: Channel 2 and 3 not shown.

6.8

µF

0.1

µF

VEE

DS015005-47

FIGURE 9. Dual Supply, A

V= + 2V/V Configuration

CLC5633IM 데이터시트(PDF) 13 Page - National Semiconductor (TI)

CLC5633IM 데이터시트(HTML) 13 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

데이터시트 다운로드

링크 URL