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ZR36060PQC 데이터시트(PDF) 38 Page - List of Unclassifed Manufacturers

부품명 ZR36060PQC
상세설명  Integrated JPEG CODEC
PDF  46 Pages
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제조업체  ETC [List of Unclassifed Manufacturers]
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Logo ETC - List of Unclassifed Manufacturers

ZR36060PQC 데이터시트(HTML) 38 Page - List of Unclassifed Manufacturers

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Integrated JPEG CODEC
AC TIMING SPECIFICATIONS
Table 7: AC Video Bus Input Timing
Symbol
Parameter
Min
Max
Unit
Comments
FVCLKx2
VCLKx2 Frequency
22.2
30
MHz
40% to 60% duty cycle
TV2P
VCLKx2 Period
33.3
45
ns
TCLK
Internal Clock Period
TV2P == 2 * TCLK
Internal PLL multiplies the VCLKx2 freq. by 2
Used as a reference variable for other AC
parameters.
TV2T
VCLKx2 Rise/Fall Transition
3
ns
TVT
VCLK Rise/Fall Transition
3
ns
TVIS
Video Bus Input Setup
6
ns
TVIH
Video Bus Input Hold
0
ns
Figure 41. Video Bus Input Timing
VCLKx2
tV2T
tV2T
tV2P
VCLK
INPUTS
tVIS
tVIH
tVIS
tVIH
Note: 1. In this diagram VCLKPol = 0.
2. 16-bit interface inputs are sampled during VCLKx2 rising edges enabled by VCLK.
3. 8-bit interface inputs are sampled during all VCLKx2 rising edges.
Table 8: AC Video Bus Output Timing
Symbol
Parameter
Min
Max
Unit
Comments
TVBO
Video Bus Output Delay (16-bit)
TCLK - 1
TCLK + 10
ns
50pf load
TVBO8
Video Bus Output Delay (8-bit)
0.5TCLK - 1
0.5TCLK + 10
ns
50pf load
Figure 42. Video Bus Output Timing
VCLKx2
VCLK
Video Output
(16-bit)
tVBO
tVBO8
Video Output
(8-bit)
tVBO
tVBO8
tCLK



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