CLC952 datasheet(7/8 Pages) NSC

7 / 8 page

AGND

(Pins 1, 6, 13) Analog circuit ground.

AVCC

(Pins 2, 12, 14) +5V power supply for the analog section. Bypass to analog ground with a 0.1

µF capacitor.

AVEE

(Pins 3, 5, 7,11) -5V power supply for the analog section. Bypass to analog ground with a 0.1

µF capacitor.

ENCODE

(Pin 4) ENCODE initiates a new data conversion cycle on each rising edge. Logic for this input is

standard TTL. 50% duty cycle is recommended for full compliance with the guaranteed specifications.

AIN

(Pin 8) Ground-centered, DC-coupled analog input with a 1Vpp maximum input range from -0.5V to

+0.5V. Analog input impedance is approximately 500

Ω.

VOFFSET

(Pin 9) Voltage offset control. Sets the midpoint of the analog input range. Normally left floating. Ratio

of applied voltage to effective offset is 200:1. (1V applied to VOFFSET produces 5mV midpoint offset.)

VREF

(Pin 10) Internal voltage reference. Nominally +2.4V. VREF can be pulled up or down with a voltage

source to program gain and input range. Bypass VREF to ground with a 0.1µF capacitor.

DVCC

(Pin 15) +5V power supply for the digital section. Bypass to digital ground with a 0.1

µF capacitor.

DGND

(Pin 16) Digital ground.

D0-D11

___

(Pins 17-28) Digital data outputs are CMOS and TTL compatible. D0 is the LSB and D11

___

is the MSB.

MSB is inverted. Output coding is two’s complement.

AGND

D11 (MSB INV)

AVCC

D10

AVEE

ENCODE

AVEE

AGND

AVEE

AIN

VOFFSET

VREF

AVEE

AVCC

(LSB)

AGND

DGND

AVCC

DVCC

CLC952

CLC952 Pin Definitions

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CLC952 데이터시트(PDF) 7 Page - National Semiconductor (TI)

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