DS1921 datasheet(31/44 Pages) DALLAS

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DS1921H/Z

31 of 44

READ/WRITE TIMING DIAGRAM Figure 15

Write-One Time Slot

RESISTOR

MASTER

VPUP

VIHMASTER

VTH

VTL

VILMAX

tSLOT

tW1L

Write-Zero Time Slot

RESISTOR

MASTER

tREC

VPUP

VIHMASTER

VTH

VTL

VILMAX

tSLOT

tW0L

Read-Data Time Slot

RESISTOR

MASTER

DS1921H/Z

tREC

VPUP

VIHMASTER

VTH

VTL

VILMAX

Master

Sampling

Window

tSLOT

tRL

tMSR

Slave to Master

A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below

VTL until the read low time tRL is expired. During the tRL window, when responding with a 0, the

DS1921H/Z will start pulling the data line low; its internal timing generator determines when this pull-

down ends and the voltage starts rising again. When responding with a 1, the DS1921H/Z will not hold

the data line low at all, and the voltage starts rising as soon as tRL is over.

The sum of tRL +

δ (rise rime) on one side and the internal timing generator of the DS1921H/Z on the

other side define the master sampling window (tMSRMIN to tMSRMAX) in which the master must perform a

read from the data line. For most reliable communication, tRL should be as short as permissible and the

master should read close to but no later than tMSRMAX. After reading from the data line, the master must

wait until tSLOT is expired. This guarantees sufficient recovery time tREC for the DS1921H/Z to get ready

for the next time slot.

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