COP685BC datasheet(17/57 Pages) NSC

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Timers (Continued)

PWM Control Register (PWMCON) (Address X’00A2)

Reserved

ESEL

PWPND

PWIE

PWMD

PWON

PWEN1

PWEN0

Bit 7

Bit 0

The PWMCON Register Bits are:

Reserved This bit is reserved and must be zero.

ESEL

Edge select bit, “1” for falling edge, “0” for rising

edge.

PWPND

PWM interrupt pending bit.

PWIE

PWM interrupt enable bit.

PWMD

PWM Mode bit, “1” for PWM mode, “0” for fre-

quency monitor mode.

PWON

PWM start Bit, “1” to start timer, “0” to stop timer.

PWEN1

Enable PWM1 output function on I/O port.

Note: The associated bits in the configuration and data register of the I/O-

port have to be setup as outputs and/or inputs in addition to setting the

PWEN bits.

PWEN0

Enable PWM0 output/input function on I/O port.

PWM Mode

The PWM timer can generate PWM signals at frequencies

up to 39 kHz (@ t

c = 1 µs) with a resolution of 255 parts.

Lower PWM frequencies can be programmed via the pres-

caler.

If the PWM mode bit (PWMD) in the PWM configuration reg-

ister (PWMCON) is set to “1” the timer operates in PWM

mode. In this mode, the timer generates a PWM signal with

DS012067-12

FIGURE 12. PWM Timer Capture Mode Block Diagram

DS012067-13

FIGURE 13. PWM Timer PWM Mode Block Diagram

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