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ICS93735 데이터시트(PDF) 1 Page - Integrated Circuit Systems |
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ICS93735 데이터시트(HTML) 1 Page - Integrated Circuit Systems |
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1 / 7 page ![]() Integrated Circuit Systems, Inc. ICS93735 0579E—08/06/03 Block Diagram DDR Phase Lock Loop Zero Delay Clock Buffer Pin Configuration 48-Pin SSOP Recommended Application: DDR Zero Delay Clock Buffer Product Description/Features: • Low skew, low jitter PLL clock driver • Max frequency supported = 266MHz (DDR 533) •I 2C for functional and output control • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • 3.3V tolerant CLK_INT input Switching Characteristics: • CYCLE - CYCLE jitter (66MHz): <120ps • CYCLE - CYCLE jitter (>100MHz): <65ps • CYCLE - CYCLE jitter (>200MHz): <75ps • OUTPUT - OUTPUT skew: <100ps • Output Rise and Fall Time: 500ps - 700ps • DUTY CYCLE: 49.5% - 50.5% Functionality FB_INT CLK_INT PLL SCLK SDATA Control Logic FB_OUTT CLKT0 CLKT1 CLKT2 CLKT3 CLKT4 CLKT5 CLKT6 CLKT7 CLKT8 CLKT9 CLKC0 CLKC1 CLKC2 CLKC3 CLKC4 CLKC5 CLKC6 CLKC7 CLKC8 CLKC9 AVDD CLK_INT CLKT CLKC FB_OUTT 2.5V (nom) L L H L on 2.5V (nom) H H L H on 2.5V (nom) < offset freq* offset freq* offset freq* offset freq* off GND L L H L Bypassed/off GND H H L H Bypassed/off * The offset frequency is ~ 20 MHz, varying somewhat from part to part. INPUTS OUTPUTS PLL State |
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