MPC875 datasheet(36/84 Pages) FREESCALE

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MPC875/MPC870 Hardware Specifications, Rev. 3.0

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Freescale Semiconductor

Bus Signal Timing

Table 11 provides the interrupt timing for the MPC875/870.

Figure 24 provides the interrupt detection timing for the external level-sensitive lines.

Figure 24. Interrupt Detection Timing for External Level Sensitive Lines

Figure 25 provides the interrupt detection timing for the external edge-sensitive lines.

Figure 25. Interrupt Detection Timing for External Edge-Sensitive Lines

Table 11. Interrupt Timing

Num

Characteristic 1

1 The I39 and I40 timings describe the testing conditions under which the IRQ lines are tested when being defined as

level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference

to the CLKOUT.

The I41, I42, and I43 timings are specified to allow correct functioning of the IRQ lines detection circuitry and have

no direct relation with the total system interrupt latency that the MPC875/870 is able to support.

All Frequencies

Unit

Min

Max

I39

IRQx valid to CLKOUT rising edge (setup time)

6.00

I40

IRQx hold time after CLKOUT

2.00

I41

IRQx pulse width low

3.00

I42

IRQx pulse width high

3.00

I43

IRQx edge-to-edge time

4xTCLOCKOUT

—

CLKOUT

IRQx

I39

I40

CLKOUT

IRQx

I41

I42

I43

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